FPGA設(shè)計的SPI自動發(fā)送模塊技術(shù)
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begin
if SPI_WR='1' then
counter8=10001;
elsif LCD_SCLSS='1' and LCD_SCLSS'event then
if counter8>0 then
counter8=counter8-1;
LCD_SCLSS8=LCD_SCLSSS;
end if;
end if;
end process;
--16bit SPI 時鐘采集生成模塊
counter16_u:process(LCD_SCLSS)
begin
if SPI_WR='1' then
counter16=100001;
elsif LCD_SCLSS='1' and LCD_SCLSS'event then
if counter16>0 then
counter16=counter16-1;
LCD_SCLSS16=LCD_SCLSSS;
end if;
end if;
end process;
--24bit SPI 時鐘采集生成模塊
counter24_u:process(LCD_SCLSS)
begin
if SPI_WR='1' then
counter24=110011;
elsif LCD_SCLSS='1' and LCD_SCLSS'event then
if counter24>0 then
counter24=counter24-1;
if (counter24=000000)or(counter24=000001)or
(counter24=110011)or(counter24=000010)then
LCD_SCLSS24='0';
else
LCD_SCLSS24=LCD_SCLSSS;
end if;
end if;
end if;
end process;
--8bit 數(shù)據(jù)移位模塊
DB8BIT_U:process(shift,SPI_WR,DBINOUTS)
begin
if SPI_WR='1' then
DB8BIT_reg=DBINOUTS(7 downto 0);
else
if shift='1' and shift'event then
LCD_SDIS_8BIT=DB8BIT_reg(0);
DB8BIT_reg(6 downto 0)=DB8BIT_reg(7 downto 1);
end if;
end if;
end process;
--16bit 數(shù)據(jù)移位模塊
DB16BIT_U:process(shift,SPI_WR,DBINOUTS)
begin
if SPI_WR='1' then
DB16BIT_reg(15 downto 0)=DBINOUTS(15 downto 0);
else
if shift='1' and shift'event then
LCD_SDIS_16BIT=DB16BIT_reg(0);
DB16BIT_reg(14 downto 0)=DB16BIT_reg(15 downto 1);
end if;
end if;
end process;
--24bit 數(shù)據(jù)移位模塊
DB24BIT_U:process(shift,SPI_WR,DBINOUTS)
begin
if SPI_WR='1' then
DB24BIT_reg(23 downto 0)=DBINOUTS(23 downto 0);
else
if shift='1' and shift'event then
LCD_SDIS_24BIT=DB24BIT_reg(0);
DB24BIT_reg(22 downto 0)=DB24BIT_reg(23 downto 1);
end if;
end if;
end process;
end;本文引用地址：http://butianyuan.cn/article/151797.htm
五、仿真波形圖
六、編譯后資源占用情況
七、結(jié)束語
本文旨在給學(xué)習(xí)可編程技術(shù)的人們提供一個參考，起到拋磚引玉的作用。望閱讀過此文的讀者提供更好的方法，與所有的學(xué)習(xí)者共享，共勉！
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