跨阻再次罷工：利用MDACs實現電流電壓轉換

　乘法D/A轉換器（MDACs）和其后置放大器搭建了數字到模擬世界的橋梁。MDACs產生與輸入數字編碼成比例的電流值（如圖1所示）。后置放大器轉換DAC輸出的電流信號為電壓值。利用DAC、放大器和電阻，簡單的電流-電壓轉換似乎很容易實現。然而，這個電路的穩(wěn)定性存在問題。

　　這樣應用，MDAC的輸出模式包括可變電流源、電阻和電容（圖1a）。輸出電阻和電容值取決于DAC的輸入編碼。一般來說，設計MDAC到0刻度會導致輸出電阻接近無窮大。設計DAC到滿量程或任意值，輸出電阻應等于反饋電阻RF值。（參見生產廠商數據手冊）。根據內部門極結點通過MDAC輸出數據，DAC的輸出電容CD也隨輸入編碼而變化。在滿量程處，MDAC的輸出電容等于數據手冊中標準值。在零點，MDAC的輸出電容等于約等于滿量程值的一半。從穩(wěn)定性考慮，使用滿量程時RD和CD的輸出值。

　　放大器反饋網絡是二階子網絡。為保證精度，大多數MDACs有一個片上反饋電阻。反饋電容CF是分開的。

　　最后，運算放大器有一系列規(guī)格指標，但對MDAC電路的穩(wěn)定性沒有影響：單位增益帶寬fU，輸入差分電容CDIF和共模電容CCM。

　　在這個系統(tǒng)中，放大器輸入的總電容等于CIN=CD+CDIF+CCM。在圖1b和圖1c中，閉環(huán)零點等于f1=1/(2π(CIN+CF)(RD||RF))。閉環(huán)極點等于f2=1/(2πCFRF)。

　　如果開放與閉環(huán)增益曲線之間的閉合速度等于20dB/decade，就能確保系統(tǒng)穩(wěn)定。為了達到這樣的效果，選擇一個單位增益帶寬小于f1或大于f2的放大器。

　　如果f1大于放大器帶寬，很容易設計出穩(wěn)定電路：

　　另一方面，如果f2低于開放與閉環(huán)增益曲線的交叉點，則使用：

　　利用這些反饋電容的計算值作為測試電路的出發(fā)點。出現電路寄生效應，器件制造偏差等問題,可以嘗試改變反饋電容值。

　　穩(wěn)定MDAC的模擬信號是關鍵。然而，也要考慮放大器的噪聲、輸入偏置電流、偏置電壓、MDAC分辨率和毛刺能量等因素。

英文原文：

　　Transimpedance strikes again: Current-to-voltage conversion with MDACs

　　Current-to-voltage conversion seems easy to implement with a DAC, amplifier, and resistor. But beware of stability issues.

　　By Bonnie Baker -- EDN, 7/5/2007

　　Multiplying DACs (MDACs) and their postamplifiers bridge the digital and analog worlds. MDACs generate a current proportional to an input digital code (Figure 1). The postamplifier converts the DAC’s current-output signal to a voltage level. A simple current-to-voltage conversion seems easy to implement with a DAC, amplifier, and resistor. However, this circuit presents stability issues.

　　For the application, the output model of the MDAC contains a variable current source, resistor, and capacitor (Figure 1a). The value of the output resistance and capacitance depends on the input code to the DAC. In general, programming the MDAC to zero scale causes the output resistance, RD, to be near infinite. When you program the DAC to full-scale or all ones, this resistance is equal to the feedback resistance, RF. (See the manufacturer’s data sheets.) The DAC’s output capacitance, CD, also varies with input code according to the number of internal gate-source junctions across the MDAC output. At full-scale, the MDAC output capacitance equals the data-sheet specification. At zero, the MDAC output capacitance is equal to about half the full-scale value. For stability calculations, use the full-scale output values of RD and CD.

　　The second subnetwork is the amplifier-feedback network. To maintain precision, most MDACs have a feedback resistor on-chip. The feedback capacitor, CF, is discrete.

　　Finally, op amps have a range of specifications, but only a few affect the MDAC circuit’s stability: unity-gain bandwidth, fU; input differential capacitance, CDIF; and common-mode capacitance, CCM.

　　In this system, total capacitance at the amplifier input is equal to CIN=CD+CDIF+CCM. In Figure 1b and Figure 1c, the closed-loop zero is equal to f1=1/(2π(CIN+CF)(RD||RF)). The closed-loop pole is equal to f2=1/(2πCFRF).

　　You ensure system stability if the rate of closure between the open- and closed-loop-gain curve equals 20 dB/decade. To do so, select an amplifier with unity-gain bandwidth of less than f1 or greater than f2.

　　It is easy to design a stable circuit if f1 is higher than the amplifier’s bandwidth:

　　Alternatively, if f2 is lower than the intersection of the open- and the closed-loop-gain curve, use:

　　CF≤–CIN+1/(2/π(RF||RD)fU).

　　Use these calculated values of feedback capacitance as starting points for your test circuit. Circuit parasitics, device-manufacturing variations, and other factors can encourage you to modify the feedback-capacitor value.

　　Stabilizing the MDAC’s analog signal is critical. However, also consider amplifier noise, input bias current, offset voltage, MDAC resolution, and glitch energy.