設計基于LED的視頻顯示板,Designing an LED
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Data frames, other than those containing PWM information, are also sent through the DVI interface utilizing a PC-based GUI. The data frame type is identified by corresponding circuits inside the FPGA. Data frames, other than those related to PWM information, have the format shown inTable 3, where HDR stands for header. Note that video frames for individual port PWM information do not contain a header.
Table 3. Video-Display Reference Design, Data-Frame Screen Format
| Row | LVDS 1 Pixel 0~63 | LVDS 2 Pixel 64~127 | LVDS 3 Pixel 128~191 | LVDS 4 Pixel 192~255 | LVDS 5 Pixel 256~319 |
| 0 | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR |
| 1 | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR |
| 2 | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... |
| ... . | ... . | ... . | ... . | ... . | |
| ... . | ... . | ... . | ... . | ... . | |
| 31 | ..Chip 1920 | ..Chip 1920 | ..Chip 1920 | ..Chip 1920 | ..Chip 1920 |
| 32 | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR |
| 33 | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR | HDR...HDR |
| 34 | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... | Chip 1 ... ... |
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