Xilinx ECU 汽車電子開發(fā)方案

Xilinx(賽靈思)公司的汽車(XA)電子控制單元(ECU)開發(fā)套件是基于賽靈思公司滿足汽車應(yīng)用標(biāo)準(zhǔn)的低成本Xilinx® XA Spartan-3E 現(xiàn)場可編程門陣列(FPGA)器件。XA 汽車 ECU套件為快速開發(fā)車內(nèi)網(wǎng)絡(luò)、信息娛樂、輔助駕駛以及駕駛信息系統(tǒng)提供了一個(gè)平臺。它該套件包括一個(gè)帶有預(yù)工程化硬件接口的開發(fā)板，支持眾多汽車應(yīng)用IP。利用這一完整的開發(fā)環(huán)境，汽車設(shè)計(jì)人員可快速完成器件評估，迅速完成設(shè)計(jì)并開始運(yùn)行。本文介紹了Xilinx的Spartan-3E FPGA系列主要性能，以及汽車電子ECU 開發(fā)套件 (HW-XA3S1600E-UNI-G)的主要性能和方框圖。

賽靈思汽車(XA)電子控制單元(ECU)開發(fā)套件是基于賽靈思公司滿足汽車應(yīng)用標(biāo)準(zhǔn)的低成本Xilinx® XA Spartan-3E 現(xiàn)場可編程門陣列(FPGA)器件。XA 汽車 ECU套件為快速開發(fā)車內(nèi)網(wǎng)絡(luò)、信息娛樂、輔助駕駛以及駕駛信息系統(tǒng)提供了一個(gè)平臺。

XA汽車ECU開發(fā)套件。該套件包括一個(gè)帶有預(yù)工程化硬件接口的開發(fā)板，支持眾多汽車應(yīng)用IP。利用這一完整的開發(fā)環(huán)境，汽車設(shè)計(jì)人員可快速完成器件評估，迅速完成設(shè)計(jì)并開始運(yùn)行。

XA 汽車 ECU開發(fā)套件提供了開發(fā)完整子系統(tǒng)所需要的所有元器件，包括配有一片XA Spartan-3E 160萬系統(tǒng)門FPGA的XA1600E開發(fā)板，板上硬件接口，如CAN 2.0B 和 C、Ethernet 10/100、USB 2.0、SPI 和 SCI。預(yù)先驗(yàn)證的賽靈思和第三方應(yīng)用IP為開發(fā)MOST® 系統(tǒng)、FlexRay 連接以及高速和低速CAN總結(jié)接口提供了必要的構(gòu)建模塊。該套件還包括一個(gè)帶有通用適配器的電源、編程和定制串行電纜、快速入門指南以及包含方便評估的參考設(shè)計(jì)的資源CD。同時(shí)還支持賽靈思嵌入式開發(fā)套件和ISE設(shè)計(jì)工具評估版。

關(guān)于XA Spartan-3E FPGA

XA Spartan-3E FPGA系列滿足大批量成本敏感汽車電子應(yīng)用要求。該系列的五款器件提供從10萬至160萬系統(tǒng)門不同密度和不同封裝組合。XA器件同時(shí)提供擴(kuò)展溫度范圍Q-Grade (-40°C 至 +125°C Tj) 和 I-Grade (-40°C 至 +100°C Tj)器件，并且符合業(yè)界公認(rèn)的AEC-Q100標(biāo)準(zhǔn)。與此前的器件相比，這些90nm器件單位美元成本提供了更多功能和I/O帶寬，在可編程邏輯行業(yè)確立了新標(biāo)準(zhǔn)。由于其超低成本，XA Spartan-3E FPGA提供了優(yōu)異的替代解決方案，避免了ASIC和ASSP的高掩膜成本和長開發(fā)周期。

一.Spartan-3E FPGA系列

The Spartan-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications.

The five-member family offers densities ranging from 100,000 to 1.6 million system gates.The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration.

These Spartan-3E enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of

conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Spartan-3E FPGA系列主要特性：

Very low cost, high-performance logic solution for high-volume, consumer-oriented applications

Proven advanced 90-nanometer process technology

Multi-voltage, multi-standard SelectIO interface pins

- Up to 376 I/O pins or 156 differential signal pairs

- LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards

- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

- 622+ Mb/s data transfer rate per I/O

- True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O

- Enhanced Double Data Rate (DDR) support

- DDR SDRAM support up to 333 Mb/s

Abundant, flexible logic resources

- Densities up to 33,192 logic cells, including optional shift register or distributed RAM support

- Efficient wide multiplexers, wide logic

- Fast look-ahead carry logic

- Enhanced 18 x 18 multipliers with optional pipeline

- IEEE 1149.1/1532 JTAG programming/debug port

Hierarchical SelectRAM memory architecture

- Up to 648 Kbits of fast block RAM

- Up to 231 Kbits of efficient distributed RAM

Up to eight Digital Clock Managers (DCMs)

- Clock skew elimination (delay locked loop)

- Frequency synthesis, multiplication, division

- High-resolution phase shifting

- Wide frequency range (5 MHz to over 300 MHz)

Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing

Configuration interface to industry-standard PROMs

- Low-cost, space-saving SPI serial Flash PROM

- x8 or x8/x16 parallel NOR Flash PROM

- Low-cost Xilinx Platform Flash with JTAG

Complete Xilinx ISE and WebPACK development system support

MicroBlaze and PicoBlaze embedded processor cores

Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices)

Low-cost QFP and BGA packaging options

- Common footprints support easy density migration

- Pb-free packaging options

二.汽車電子ECU 開發(fā)套件 (HW-XA3S1600E-UNI-G)

The Automotive ECU Development Kit (HW-XA3S1600E-UNI-G) is a configurable and extensible platform suited for a wide range of automotive applications right out of the box.

圖1。汽車電子ECU 開發(fā)套件外形圖

With its small form factor, it can be easily placed in standard metal housing. The board was designed to be powered by a 12-volt power supply for in-vehicle prototype use. Powered by a completely field-configurable Spartan-3E FPGA platform, this kit:

Combines programmable logic for custom driven IP applications with the Xilinx MicroBlaze32-bit microprocessor core.

Features robust memory subsystem containing on-board Flash and SRAM memory.

Supports standard Automotive and System-on-chip peripherals including all necessary physical layers on board the ECU, such as JTAG, 10/100 Ethernet, USB 2.0, 12-bit ADC, High and Low Speed CAN, FlexRay, LIN, K-Line, UART, SPI and over 150 user programmable I/Os.

ECU 開發(fā)套件包括：

XA1600E development board with the XC3S1600EFG484 device

Power supply with universal adaptor

Programming cable

Custom serial cable

QuickStart guide

EDK and ISE evaluation tools

Resource CD with reference designs for easy evaluation

ECU 開發(fā)套件主要特性：

Xilinx device: XC3S1600EFG484 FPGA

Complete out-of-the box development system

On-board hardware interfaces such as CAN 2.0C, Ethernet 10/100, USB 2.0, SPI, and SCI

Support for pre-verified Xilinx and Partner IP for High and Low Speed CAN, FlexRay and MOST® network interfaces.

Daughter card is required for MOST interface.

圖2。ECU 開發(fā)板方框圖