LPCVD TEOS 厚度的機(jī)械應(yīng)力對(duì)閃存循環(huán)性能的影響

　　從實(shí)驗(yàn)中可知，由于通過減小LPCVD TEOS厚度改進(jìn)循環(huán)Vt漂移對(duì)PCM、fLWR及良品率無負(fù)面影響，LPCVD TEOS目標(biāo)厚度即于2009年12月份從12.5nm改成11.5nm。

　　結(jié)論

　　為了保證最終用戶能獲得高度可靠的NVM(非易失性存儲(chǔ)器)，改進(jìn)循環(huán)(耐久性)性能極其重要。本研究得出了一個(gè)非常有趣的結(jié)論：LPCVD TEOS厚度可影響閃存循環(huán)Vt漂移。將TEOS厚度從12.5nm降至11.5nm，有助于在700k的P/E循環(huán)之前針對(duì)讀取失敗獲取更多制程裕度：TEOS厚度減小1nm，制程裕度增大約20mV。

　　工作展望

　　從多個(gè)DOE批次的實(shí)驗(yàn)中可知，NVM循環(huán)性能可能受到許多制程的影響，包括HTN RF功率、FSI清洗速度、RTP側(cè)壁氧化厚度、IMD配方、以及LPCVD TEOS厚度。而且，如圖8所示，在SCTEOS厚度降至11.5nm后，循環(huán)Vt所受的影響并不明顯，這和我們?cè)?個(gè)DOE批次被分別實(shí)驗(yàn)的圖3b中看到的一樣。這表明，除LPCVD TEOS厚度外，還有其他制程也會(huì)影響Vt漂移。然而，如今我們還未完全弄清楚影響Vt漂移的決定性因素。因此，弄明白可以優(yōu)化NVM P/E循環(huán)性能同時(shí)不影響其他電學(xué)參數(shù)的方法及工藝窗口很重要。循環(huán)失敗的根本原因探索之旅仍在繼續(xù)。為了在循環(huán)性能上獲取更多制程裕度，我們同時(shí)開展了許多工作。

　　此外，借助透射式電子顯微鏡(TEM)利用會(huì)聚束電子衍射(CBED)測量閃存單元中的局部應(yīng)力這一內(nèi)部方法，對(duì)于以后的研究也很有用。

      
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